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Microchip Technology /ATSAMV71J20 /DACC /IDR

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Interpret as IDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXRDY0)TXRDY0 0 (TXRDY1)TXRDY1 0 (EOC0)EOC0 0 (EOC1)EOC1

Description

Interrupt Disable Register

Fields

TXRDY0

Transmit Ready Interrupt Disable of channel 0
TXRDY1

Transmit Ready Interrupt Disable of channel 1
EOC0

End of Conversion Interrupt Disable of channel 0
EOC1

End of Conversion Interrupt Disable of channel 1

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data